本项目目的在于，基于目前现有的嵌入式部件的安全功能（Spartan-3A的Device DNA和中兴TCM芯片），提供一个保证嵌入式系统程序完整性的设计方案。于此同时，参照可信计算规范标准，为嵌入式系统打造一个可信根，为之后的可信链的建立及嵌入式可信平台的构造提供必要的条件。最终满足国内嵌入式系统安全需求，并为我国嵌入式系统可信技术独立自主发展提供支持。

Integrity verification is one of the requirements of the trusted computing specification that published by the TCG (trust computing group). It is necessary to provide a scalable integrity certification scheme for different embedded systems. The Integrity-verified Flash Controller (IFC) provides such integrity verification capability for embedded systems by considering the power consumption, resource and efficiency. With the SHA-1 encryption algorithm engine, the standard secure message digest algorithm defined in RFC 3174, it can provide the fast, stable, and high compatible service across many processor architectures, especially for PowerPC. Before the processor fetches instructions from off-chip flash memory, IFC should scan specific flash sections and compute its digest value with SHA-1 engine. By checking the result provided by IFC that indicates whether the message digest is equal the pre-defined value or not, system software can affirm whether the specific flash sections is tempered with or not. Such correct flash sections become the trusted root.
As an IP core, the IFC is firstly designed based on Xilinux FPGA, aiming to communicate with the PowerPC core through PLB interface, which is a part of the Core Connect bus protocol in Power SoC architecture. At present, we have applied the design for an ARM-based platform. That is, the purposed design is suitable to the embedded systems and gets the universality through some slightly adjustments.